1. Field of the Invention
The present invention relates to digital circuit timing accuracy and, more particularly, to techniques for using hold cells in low power oscillators to maintain long-term timing accuracy in sleep mode without reliance on an external crystal.
2. Description of the Related Art
It is common for today""s electronic devices to incorporate combinations of analog and digital circuitry. Many of these devices, such as cellular phones, operate in mobile environments where design characteristics are being pushed to meet higher consumer demands. These demands include smaller, more compact devices with longer battery life at a lower overall cost. In order to meet these demands, analog and digital circuitry should be combined more efficiently and in a manner that will reduce power consumption.
In an attempt to conserve power, many devices implement a sleep mode when not in use. It is known, for example, that incorporation of a sleep mode in cellular phone devices may extend battery life by up to a factor of 10. A key objective when designing portable electronic devices is to minimize the amount of current used while in sleep mode. In addition to minimizing the amount of current used while in sleep mode, the device should also be able to retain some level of timing accuracy for a minimum duration as dictated by the application.
To maintain the required level of timing accuracy while in sleep mode, most devices use a sleep mode oscillator. It is common in modem designs to use a low-power, low-frequency crystal on the printed circuit board for the sleep mode oscillator. This low-power crystal is external to the semiconductor chips and is present in addition to an external master crystal which is used during normal operation.
FIG. 1, while not to scale, shows a prior art printed circuit board (PCB) device 101, including a semiconductor chip 103, an external master crystal 115, and an external low-power crystal 117. The semiconductor chip 103 may contain a digital core 105, an analog component 107, a digital component 109, a radio frequency (RF) component 111, or other circuitry 113. The semiconductor chip 103 receives a signal 119 from either the master crystal 115 or the low-power crystal 117, depending on the mode of operation.
The use of the second external low-power crystal 117 presents several disadvantages relative to design optimization. An obvious disadvantage is that the second external low-power crystal 117 takes up valuable space on the PCB device 101. FIG. 1 is not to scale; in actuality the external master crystal 115 and external low-power crystal 117 are of relatively large size, comparable to the size of the semiconductor chip 103 itself. Therefore, addition of the second external low-power crystal 117 can be significant to overall PCB device 101 size. Another disadvantage is that adding the second external low-power crystal 117 increases the expense of the overall PCB device 101. A less obvious disadvantage is that the external low-power crystal 117 requires the semiconductor chip 103 to have a pin available for interface connection. As the semiconductor chip 103 has a limited number of pins available, dedication of a pin to the external low-power crystal 117 may be costly relative to design restrictions and complications. Furthermore, the routing required to connect the semiconductor chip 103 to the external low-power crystal 117 uses valuable PCB device 101 area and adds expense. Two objectives in the industry are to move toward smaller devices and minimize cost. Adding the second external low-power crystal 117 to the PCB device 101 does not comply with these two objectives. Therefore, the focus of attention is to remove the external low-power crystal 117 used to support the sleep mode of operation.
FIG. 2 shows the PCB device 101 from FIG. 1 with the external low-power crystal 117 removed. Additionally, FIG. 2 shows a low power oscillator (LPO) 121 receiving a clock reference signal 123 from the external master crystal 115 and providing a low frequency output signal 125 to the digital core 105. As a substitute for the external low-power crystal 117, one requirement of the LPO 121 is to derive a lower frequency signal from a higher frequency signal. The temperature stability of the LPO 121 is a typical consideration when replacing the external low-power crystal 117. A feature of an on-board crystal is that changes in frequency due to changes in temperature are minimized, whereas a free-running oscillator will change in frequency significantly with temperature. However, one known method for designing the LPO 121 to be temperature stable is to use a conventional phase lock loop (PLL) 122, as shown in FIG. 3.
FIG. 3 shows the conventional PLL 122 used to derive a lower frequency signal from a higher frequency signal. The conventional PLL 122 takes an accurate clock reference signal 123 from the external master crystal 115. The clock reference signal 123 is passed to a reference divider 129, via a connection 127, which divides the clock reference signal 123 down to a lower frequency signal. The output signal from the reference divider 129 is then passed to a phase frequency detector (PFD) 133 via a connection 131. The PFD 133 generates an output signal which is passed through a connection 135 to control a charge pump 137. The charge pump 137, in turn provides an output signal which is passed through a connection 139 to control a voltage controlled oscillator (VCO) 145. The VCO 145 provides a low frequency output signal 125 from the conventional PLL 122 via a connection 146. The VCO 145 low frequency output signal 125 is also passed to an N-counter 149, via a connection 147. The N-counter 149 generates an output signal which is provided to the PFD 133 via a connection 151. An N value of the N-counter 149 can be set arbitrarily; however, the N value remains fixed. Due to the conventional PLL 122 functionality, the VCO 145 output frequency is equal to the N value of the N-counter 149 times the N-counter 149 output frequency. The conventional PLL 122 function is to make both input signals to the PFD 133 match in both frequency and phase. The PFD 133 makes a decision on whether or not the VCO 145 output signal frequency should be higher or lower, depending on what is required to match the reference input signal frequency, received through connection 131, to the N-counter 149 output signal frequency received through connection 151. Thus, the conventional PLL 122 is a closed-loop, negative feedback circuit.
Due to the way the PFD 133 functions and the accuracy of the clock reference signal 123 entering the PFD 133 via the reference divider 129, the accuracy of the VCO 145 low frequency output signal 125 will equal the accuracy of the clock reference signal 123. Therefore, obtaining a desired low frequency output signal 125 accuracy is accomplished by requiring the clock reference signal 123 to have a better accuracy. In reality, external master crystal 115 accuracies are typically xc2x120 ppm which is sufficient for LPO 121 applications requiring output signal accuracies up to xc2x120 ppm.
Through use of the conventional PLL 122 featuring closed-loop, negative feedback, the consistent low frequency output signal 125 is derived from the clock reference signal 123 and is maintained regardless of changes in temperature. Thus, the closed-loop, negative feedback conventional PLL 122 alleviates the need for the additional external low-power crystal 117 to produce a low frequency reference clock signal to be used in sleep mode. However, power conservation while in sleep mode requires that the external master crystal 115 be turned off.
One feature of the conventional PLL 122 is that it has a flywheel effect. This means that once the loop is locked, if the loop is broken, the output of the VCO 145 will stay at the same frequency for a short period of time. This stems from the fact that as long as a voltage V, as shown in FIG. 3, at the input to the VCO 145 remains constant, the output frequency from the VCO 145 will remain constant. To take advantage of the conventional PLL 122 flywheel effect when the master crystal 115 is turned off, such as when entering sleep mode, the input voltage to the VCO 145 should be maintained at a constant level.
FIG. 4 shows the conventional PLL 122 in an opened state where the clock reference signal 123, the reference divider 129, the PFD 133, the charge pump 137, and the N-counter 149 are turned off as indicated by a slash 153. As shown in FIGS. 3, 4, and 5, the conventional PLL 122 incorporates a loop filter 144 at input connection 139 to the VCO 145. The loop filter 144 includes a resistor 141 coupled to a capacitor 143. The coupling of resistor 141 and capacitor 143 serves to stabilize the input voltage V to the VCO 145. Opening of the conventional PLL 122 may be thought of as a switch 155, as shown in FIG. 5, to the input of the VCO 145.
FIG. 5 shows the circuit diagram of the conventional PLL 122 between the charge pump 137 and the VCO 145. Switch 155 is in line with connection 139 which provides input to the VCO 145. The coupled resistor 141 and capacitor 143 are in line with the input to the VCO 145 to facilitate maintaining a constant VCO 145 input voltage V. If the switch 155 were considered ideal and the voltage V at the input to the VCO 145 were to remain constant, the frequency of the low frequency output signal 125 would remain constant. Unfortunately, due to tolerances and imperfections in the complementary metal oxide silicon (CMOS) process used to make semiconductor chips, a leakage current I1 159 and a leakage current I2 161 flow from the capacitor 143 through parasitic P-N junction diodes on the silicon. Also, leakage currents flowing through parasitic P-N junction diodes within the VCO 145 are symbolized by the presence of a diode 157 in FIG. 5. Thus, the presence of leakage current is simply due to the nature of the CMOS process used to create semiconductor chips.
Even though leakage currents through the parasitic P-N junction diodes are very small, they can have a significant effect on the voltage V at the input to the VCO 145. The high sensitivity of the VCO 145 input voltage V to leakage currents I1 159 and I2 161 is partially due to the high impedance present when looking through a node 140 toward the entrance of the VCO 145 and back toward the switch 155. Furthermore, due to the high gain (i.e., Hz/V) of a typical VCO 145, a small change in current may cause a change in the VCO 145 input voltage V sufficiently large to in turn cause the VCO 145 output frequency to fall outside of an acceptable range. For example a typical VCO 145 may have a gain of 20 kHz per Volt. If this typical VCO 145 requires an output frequency accuracy of xc2x14 Hz, a change in VCO 145 input voltage V of more than 0.2 mV will cause the VCO 145 output frequency to be unacceptable. The time required for the leakage currents I1 159 and I2 161 to cause an unacceptably large change in VCO 145 input voltage V is typically very short (i.e., less than one second). This basically means that a device using a conventional PLL 122 would be required to return from sleep mode quite frequently (i.e., about every second or less) despite the absence of a user operation signal. If the device has sufficient computing capability and battery life, a frequency hold time (i.e., sleep mode duration) of less than one second may be tolerable. However, for small mobile devices that are limited in computing power by variables such as cost, size, and power consumption, it is desirable to have the capability of maintaining longer sleep mode operation times (i.e., longer VCO 145 input voltage V hold times).
In view of the foregoing, there is a need for a device that avoids the problems of the prior art by providing a temperature-stable, low power consumption, CMOS process implementable, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation times in systems where optimization of size, cost, and battery life are paramount.
Broadly speaking, the present invention fills these needs by providing methods and apparatuses for an analog hold cell that can be used in a low power oscillator to generate an accurate reference clock signal to support a long sleep mode operation time in an electronic device. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several embodiments of the present invention are described below.
In one embodiment, a low power oscillator is disclosed. The low power oscillator includes a voltage controlled oscillator having an input and an output. The output of the voltage controlled oscillator provides a signal of substantially constant frequency that can be used by a host electronic device during a sleep mode (i.e., low-power mode) of operation. During the sleep mode of operation, the voltage controlled oscillator receives its input from a hold cell. The hold cell provides a differential voltage as the input to the voltage controlled oscillator. The hold cell incorporates a common mode voltage feedback to control a common mode voltage associated with the differential input voltage supplied to the voltage controlled oscillator. The common mode voltage feedback control assists in maintaining the differential input voltage supplied to the voltage controlled oscillator at a substantially constant level. Thus, allowing the voltage controlled oscillator to generate an output signal of substantially constant frequency during low-power operation of the host electronic device.
In another embodiment, a hold cell is disclosed. The hold cell includes hold circuitry that provides a differential output voltage. The hold circuitry is in electrical communication with control circuitry. The control circuitry receives a common mode voltage from the hold circuitry and compares the common mode voltage to a reference voltage. A difference between the common mode voltage and the reference voltage is used by the control circuitry to generate a feedback signal that is sent from the control circuitry to variable current source circuitry. The variable current source circuitry provides a current to the hold circuitry based on the feedback signal received from the control circuitry. The current provided from the variable current source circuitry to the hold circuitry is used to adjust the common mode voltage provided by the hold circuitry such that the difference between the common mode voltage and the reference voltage is negated.
In yet another embodiment, a method for providing a substantially constant differential voltage is disclosed. The method includes storing a voltage on a first hold stage and a second hold stage. A differential output voltage is then generated by the first hold stage. The method further includes refreshing the voltage stored on the second hold stage with the voltage stored on the first hold stage. The differential output voltage previously generated by the first hold stage is replaced with a differential output voltage generated by the second hold stage. The method further includes refreshing the voltage stored on the first hold stage with the voltage stored on the second hold stage. The differential output voltage previously generated by the second hold stage is then replaced with a differential output voltage generated by the first hold stage. Refreshing of the voltages on the first and second hold stages and the alternation of the differential output voltage generation responsibility between the first and second hold stages continues in the aforementioned manner until a signal requires the method to revert back to storing a voltage on the first hold stage and the second hold stage. While performing the method, the generated differential output voltage remains substantially constant.
The advantages of the present invention are numerous. The hold cell incorporated into a low power oscillator as disclosed in the present invention provides a device and method for generating an accurate reference clock signal. The accurate reference clock signal can be used to support long sleep mode operation times. Furthermore, the present invention avoids the problems of the prior art by providing a temperature-stable, low power consumption, CMOS process implementable, size-efficient method for generating the accurate reference clock signal. Thus, the advantages of the present invention are especially useful in systems where optimization of size, cost, and battery life are paramount.
Other aspects and advantages of the invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the present invention.